Timing analysis of the Seidel-Even FP-ADD algorithm

This project deals with the implementation and timing analysis of a Floating-Point Adder design. The implementation is based on a paper “On the Design of Fast IEEE Floating-Point Adders”, written by Peter-M. Seidel and Guy Even.

The FP-Adder RTL design was written in Verilog hardware description language, it was simulated using Cadence NC-Verilog simulator and synthesized using Synopsys Design Compiler.

The functional verification of the design was based on an exhaustive set of test vectors generated using s2b-api software written by Shahr Bar-Or. The expected results were calculated using MATLAB software written by Arnon Warshavski and Eran Eidinger with some modifications.

The test vectors were injected by a test-bench and the simulation results were compared against the expected pre-calculated results in order to approve the correct functionality of the FP-add design.

The timing analysis was based on the Synopsys DC’s timing reports.

Using UMC's 0.15-micron process technology library (UMC015) we got the following results:

Pipeline stage	Critical path source	Critical path destination	delay	Normalized delay
1^st cycle	EA[0]	FOPSUM[6]	2.61 [nsec]	9.6 [logic level]
2^nd cycle	P[33]	Eout[10]	3.89 [nsec]	14.4 [logic level]

From the table it can be seen that the FP-add can operate in 250 MHz.

The FP-add design can be converted easily into one stage pipeline, with delay of approximately 6.5 [nsec] which means ~150 Mhz.

Project database structure

The database structure includes four directories:

RTL sources: src

RTL simulation: sim

RTL test vectors: stimulus

Synthesis: synth

src directory

This directory includes a verilog description of the:

• N_path - includes RTL description of the N_path: src\N_path

• R_path - includes RTL description of the R_path: src\R_path

• top - includes RTL description of the top level: src\top

sim directory

This directory includes:

• testbench: sim\fp_adder_tst.v

• script which invoke the NC-Verilog simulator: sim\run_test_top

• A list of all RTL file which should be compiled by the simulator: sim\design_env_top.def

• A subdirectory where simulation result is located in: sim\run_results

stimulus directory

This directory includes the input test vectors and expected results. These files were read by the testbench.

• Inputs:

• significand of operand A: stimulus\fa.txt
• significand of operand B: stimulus\fb.txt
• exponent of operand A: stimulus\ea.txt
• exponent of operand B: stimulus\eb.txt
• sign of operand A: stimulus\sa.txt
• sign of operand B: stimulus\sb.txt
• rounding mode: stimulus\rnd.txt
• operation - sop: stimulus\op.txt

• Expected results:

• significand of the sum: stimulus\fo.txt
• exponent of the sum: stimulus\eo.txt
• sign of the sum: stimulus\so.txt

The text files stimulus\fpadd_in1.txt and stimulus\fpadd_out1.txt include inputs and expected results vectors from where the entire list above was extracted.

synth directory

This directory includes four sub-directories each includes a synthesis script and a verilog netlist:

• synth\N_path
• synth\R_path
• synth\Path_sel
• synth\FP_adder_top

A summery of the timing results were summarized in the files:

• short_results.inp2FF.xls
  Timing results from input to first sampling stage.
  
  

• short_results.FF2out.xls
  Timing results from first sampling stage to output.

Ronen Goldberg

Moshe Sherman