Timing analysis of the Seidel-Even FP-ADD algorithm

This project deals with the implementation and timing analysis of a Floating-Point Adder design. The implementation is based on a paper “On the Design of Fast IEEE Floating-Point Adders”, written by Peter-M. Seidel and Guy Even.


The FP-Adder RTL design was written in Verilog hardware description language, it was simulated using Cadence NC-Verilog simulator and synthesized using Synopsys Design Compiler.


The functional verification of the design was based on an exhaustive set of test vectors generated using s2b-api software written by Shahr Bar-Or. The expected results were calculated using MATLAB software written by Arnon Warshavski and Eran Eidinger with some modifications.

The test vectors were injected by a test-bench and the simulation results were compared against the expected pre-calculated results in order to approve the correct functionality of the FP-add design.


The timing analysis was based on the Synopsys DC’s timing reports.


Using UMC's 0.15-micron process technology library (UMC015) we got the following results:


Pipeline stage

Critical path source

Critical path destination


Normalized delay

1st cycle



2.61 [nsec]

9.6 [logic level]

2nd cycle



3.89 [nsec]

14.4 [logic level]


From the table it can be seen that the FP-add can operate in 250 MHz.

The FP-add design can be converted easily into one stage pipeline, with delay of approximately 6.5 [nsec] which means ~150 Mhz.   



Project database structure


The database structure includes four directories:

RTL sources:             src

RTL simulation:         sim

RTL test vectors:       stimulus

Synthesis:                  synth


src directory

This directory includes a verilog description of the:



sim directory

This directory includes:


stimulus directory

This directory includes the input test vectors and expected results. These files were read by the testbench.


The text files stimulus\fpadd_in1.txt and stimulus\fpadd_out1.txt include inputs and expected results vectors from where the entire list above was extracted.


synth directory

This directory includes four sub-directories each includes a synthesis script and a verilog netlist:


A summery of the timing results were summarized in the files:



Ronen Goldberg

Moshe Sherman