The web page summarizes some of the work I have been involved with
regarding the design of IEEE compliant floating-point adders.
The most recent paper (not published yet) is the following paper:
On the Design of Fast IEEE Floating-Point
Previous versions (with somewhat weaker results) are listed below:
- Peter-M. Seidel and Guy Even, ``How many logic levels does
floating-point addition require?'' Proceedings of the 1998
International Conference on Computer Design (ICCD'98)): VLSI in
Computers & Processors, pp. 142-149, Austin, Texas, Oct. 1998.
- Peter-M. Seidel and Guy Even, ``On the design of fast IEEE
Floating-Point Adders'', in Proceedings 15th IEEE Symposium on
Computer Arithmetic, pp. 184 -194, 2001.
- Supporting De-normalized Numbers in an IEEE
Compliant Floating-Point Adder Optimized For Speed
- A Visualization
tool. A simulator was built using
Visual Basic 6.0 by Arnon Warshavski and Boaz Ur. The simulator was
tested by Eran Eidinger and Tal Roll.
Bar-Or. An exhaustive set of test vectors for small precision was
transformed to a set of test vectors for double precision. This
transformation preserves all observable ``combinations'' of control
signals (i.e. signals that do not depend on the precision of the
The FP-Adder RTL design was written in Verilog hardware description
language, simulated using Cadence NC-Verilog simulator, and
synthesized using Synopsys Design Compiler.